The present invention relates to vertical power semiconductor devices that facilitate a high breakdown voltage and a high current capacity, such as MOSFET (insulated gate field effect transistors), IGBT (conductivity-modulation-type MOSFET), bipolar transistors and diodes. The present invention relates also to the method of manufacturing such semiconductor devices.
Semiconductor devices may be roughly classified as lateral devices that arrange electrodes on a major surface, or vertical devices that distribute electrodes on both major surfaces facing opposite to each other. When a vertical semiconductor device is ON, a drift current flows in the thickness direction of the semiconductor chip (vertical direction). When the vertical semiconductor device is OFF, the depletion layers caused by applying a reverse bias voltage expand also in the vertical direction.
FIG. 28 is a cross sectional view of a conventional planar-type n-channel vertical MOSFET. Referring to FIG. 28, the vertical MOSFET includes an n+-type drain layer 11 with low electrical resistance, a drain electrode 18 in electrical contact with n+-type drain layer 11, a highly resistive nxe2x88x92-type drain drift layer 12 on n+ drain layer 11, p-type base regions 13 formed selectively in the surface portion of nxe2x88x92-type drain drift layer 12, a heavily doped n+-type source region 14 formed selectively in p-type base region 13, a heavily doped p+-type contact region 19 formed selectively in p-type base region 13, a gate insulation film 15 on the extended portion of p-type base region 13 extended between n+-type source region 14 and n-type drain drift layer 12, a gate electrode layer 16 on gate insulation film 15, and a source electrode 17 in electrical contact commonly with n+-type source regions 14 and p+-type contact regions 19.
In the vertical semiconductor device shown in FIG. 28, highly resistive nxe2x88x92-type drain drift layer 12 works as a region for making a drift current flow vertically when the MOSFET is in the ON-state. In the OFF-state of the MOSFET, n-type drain drift layer 12 is depleted by the depletion layers expanding from the pn-junctions between drain drift layer 12 and p-type base regions 13 to obtain a high breakdown voltage. Thinning highly resistive nxe2x88x92-type drain drift layer 12, that is shortening the drift current path, is effective for substantially reducing the on-resistance (resistance between the drain and the source) of the MOSFET, since the drift resistance is lowered in the ON-state of the device. However, when the drift current path in nxe2x88x92-type drain drift layer 12 is shortened, the space between the drain and the source, into that the depletion layers expand from the pn-junctions between p-type base regions 13 and n-type drain drift layer 12 in the OFF-state of the device, is narrowed and the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon. Therefore, breakdown is caused before the voltage between the drain and the source reaches the designed breakdown voltage of the device.
A high breakdown voltage is obtained by thickening nxe2x88x92-type drain drift layer 12. However, a thick nxe2x88x92-type drain drift layer 12 inevitably causes high on-resistance and loss increase. In short, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage of the MOSFET. The tradeoff relation exists in other semiconductor devices, such as IGBT, bipolar transistors and diodes, which include a drift layer.
European Patent 0 053 854, U.S. Pat. Nos. 5,216,275, 5,438,215, Japanese Unexamined Laid Open Patent Application H09(1997)-266311 and Japanese Unexamined Laid Open Patent Application H10(1998)-223896 disclose semiconductor devices, which include an alternating conductivity type drift layer formed of heavily doped vertical n-type regions and vertical p-type regions alternately laminated horizontally with each other.
FIG. 29 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring to FIG. 29, the vertical MOSFET of FIG. 29 is different from the vertical MOSFET of FIG. 28 in that the vertical MOSFET of FIG. 29 includes an alternating conductivity type drain drift layer 22, that is not a single-layered one but formed of n drift current path regions 22a and p partition regions 22b alternately laminated horizontally with each other. Even when the impurity concentrations in the alternating conductivity type layer are high, the alternating conductivity type layer facilitates obtaining a high breakdown voltage, since depletion layers expand laterally from the pn-junctions extending vertically across the alternating conductivity type layer in the OFF-state of the device, completely depleting drain drift layer 22.
Hereinafter, the semiconductor device including an alternating conductivity type drain drift layer will be referred to as the super-junction semiconductor device.
In the super-junction semiconductor device, a high breakdown voltage is obtained in the alternating conductivity type drain drift layer beneath p-type base regions 13 (an active region of the device) formed in the surface portion of the semiconductor chip. However, the electric field strength in the depletion layers soon reaches the maximum (critical) value for silicon in the circumferential region of the alternating conductivity type drain drift layer (the peripheral region of the device), since the depletion layers from the pn-junction between drain drift layer 22 and the outermost p-type base region 13 does not completely expand outward nor to the bottom of the semiconductor chip. Therefore, the local breakdown voltage in the peripheral region of drain drift layer 22, that is the local breakdown voltage in the peripheral region of the device, is not high enough.
The conventional guard ring formed for controlling the depletion electric field on the peripheral surface portion of the device or the conventional field plate structure formed for controlling the depletion electric field on the insulation film may be used to obtain a high local breakdown voltage in the peripheral region of the device adjacent to the outermost p-type base region 13. It is difficult, however, to optimize the integral structure integrating the alternating conductivity type drain drift layer 22 for obtaining a higher breakdown voltage and the conventional guard ring or the conventional field plate for obtaining a certain local breakdown voltage in the peripheral region of the device. In other words, it is difficult to correct the depletion electric field by an external means added from outside such as the integral structures described above. The reliability of semiconductor device having such an external means for correcting depletion electric field is not high. Since the deep portion of the device spaced apart from the guard ring is not depleted, the local breakdown voltage in the peripheral region of the device is not so high as the breakdown voltage in the drain drift layer 22. Therefore, the conventional guard ring or the conventional field plate is not effective to provide the entire device structure with a high breakdown voltage nor to fully utilize the functions of the alternating conductivity type drain drift layer. It is also necessary to employ the steps of forming masks for realizing the integral structure, implanting impurity, driving the implanted impurity atoms, depositing metal films, patterning the deposited metal films and such additional steps for manufacturing the super-junction semiconductor device.
It is an object of the present invention to provide a super-junction semiconductor device that facilitates providing the peripheral region thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate.
It is still another object of the invention to provide the manufacturing methods suitable for manufacturing the super-junction semiconductor devices described above.
To achieve this and other objects of the present invention, a semiconductor device comprises a semiconductor chip having a first major surface and a second major surface opposing the first major surface; an active region on a side of the first major surface; a layer of a first conductivity type on a side of the second major surface, the layer of the first conductivity type exhibiting relatively low electrical resistance; a first main electrode electrically connected to the active region; a second main electrode electrically connected to the layer of the first conductivity type; a drain drift region between the active region and the layer of the first conductivity type, the drain drift region providing a vertical drift current path in the ON-state of the device and being depleted in the OFF-state of the device; and a breakdown withstanding region around the drain drift region and between the first major surface and the layer of the first conductivity type, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device, the breakdown withstanding region comprising an alternating conductivity type layer comprising first regions of the first conductivity type and second regions of a second conductivity type, the first regions and the second regions being arranged alternately with each other.
According to another aspect of the present invention, a semiconductor device comprises a semiconductor chip having a first major surface and a second major surface opposing the first major surface; an active region on a side of the first major surface; a layer of a first conductivity type on a side of the second major surface, the layer of the first conductivity type exhibiting relatively low electrical resistance; a first main electrode electrically connected to the active region; a second main electrode electrically connected to the layer of the first conductivity type; a drain drift region between the active region and the layer of the first conductivity type, the drain drift region providing a vertical drift current path in the ON-state of the device and being depleted in the OFF-state of the device; and a breakdown withstanding region around the drain drift region and between the first major surface and the layer of the first conductivity type, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device, the breakdown withstanding region comprising a highly resistive region doped with an impurity of the first conductivity type and an impurity of the second conductivity type.
According to yet another aspect of the present invention, there is a method of manufacturing a semiconductor device. The method comprises (a) growing a highly resistive first epitaxial layer of a first conductivity type on a semiconductor substrate of the first conductivity type, the semiconductor substrate exhibiting relatively low electrical resistance; (b) selectively implanting an impurity of the first conductivity type into the first epitaxial layer through first windows and an impurity of a second conductivity type into the first epitaxial layer through second windows, the first windows and the second windows being arranged alternately with each other and spaced apart from each other regularly; (c) growing a highly resistive second epitaxial layer of the first conductivity type on the first epitaxial layer; (d) repeating the steps (b) and (c); and (e) thermally driving the implanted impurities from the diffusion centers thereof, whereby to connect unit diffusion regions of the same conductivity type vertically and whereby to form the first alternating conductivity type layer and the second alternating conductivity type layer.
According to yet another aspect of the present invention, there is a method of manufacturing a semiconductor device. The method comprises (a) growing a highly resistive first epitaxial layer of a first conductivity type on a semiconductor substrate with low electrical resistance; (b) implanting an impurity of the first conductivity type into the entire surface portion of the first epitaxial layer and selectively implanting an impurity of a second conductivity type into the first epitaxial layer through windows spaced apart from each other regularly; (c) growing a highly resistive second epitaxial layer of the first conductivity type on the first epitaxial layer; (d) repeating the steps (b) and (c); and (e) thermally driving the implanted impurities, whereby to connect unit diffusion regions of the second conductivity type vertically and whereby to form the first alternating conductivity type layer and the second alternating conductivity type layer.